Y Ddraig hardware
CPU, RAM and ROM
The CPU used by Y Ddraig is the Motorola MC68000 running at 10 MHz. The 68000 has a 16-bit data bus and 24-bit address bus internally runs as a full 32-bit machine. The 68000 has 8 general purpose data registers D0-D7 and 8 address registers A0-A7. The address register A7 is also used as a special purpose register holding the stack pointer.
There is 512K of ROM available supplied by two 256K x 8-bit SST39SF020 devices for the ODD and EVEN addresses.
RAM is provided by two 512K x 8-bit AS6C4008 Static RAM devices giving a total of 1024K of available memory. There is also the option of adding an additional Dynamic RAM to expand the memory up to a total of 9MB.
As the MC68000 is a memory mapped device the address decoding is handled by a Xilinx XC95C108 CPLD. In addition to the address decoding the CPLD is also used as the DRAM controller.
The memory map is as follows:
|Device||Start Address||End Address|
Y Ddraig support up to a maximum of 8MB Dynamic RAM via two 4MB 30-Pin SIMMs. Smaller values can be used but both SIMMS must be of the same type.
The XC95108 CPLD handles read and write access to the DRAM and handles the CAS-before-RAS refresh. Any wait states that have to be added are done using the DRAM DTACK signal.
A RS-232 serial port is provided using a MC68681 Dual Universal Asynchronous Receiver/Transmitter. Although two channels are available in the DUART only a single channel is being used on this design.
Timer and parallel port
A MC68230 Parallel Interface/Timer is used to provide a programmable timer and the parallel port interface.
Keyboard and mouse
The keyboard and mouse are connected via the two PS/2 ports at the rear of the computer and are controlled by a VT82C42 keyboard controller, an 80C42 compatible device.
The IDE interface provides a 16-bit connection to allow a hard drive or a compact flash card (with suitable adaptor) to be used for mass storage. A jumper link connected to pin 20 allows 5 volts to be supplied if using a CF card which is supported by several CF adaptor interfaces.
The RTC is provided by a 4-bit RTC-72421. A battery backup is provided so that the date and time is not lost when the computer is switched off.
There are 4 expansion slots on the board. Each slot is mapped to a range of memory with 1 Meg allocated to each slot. Access for any devices is currently done through this memory range. There is an additional range of 256 bytes of memory that is currently only used to ID the board connected to the slot. Reading from any address in this range will return an 8-bit ID value for the connected board. The functionality for the ID could be expanded in the future if required.
Expansion slots 1-3 can generate interrupts to the CPU but slot 4 doesn’t support interrupts.
The pinout on the expansion slots are as follows:
There are three input pins available on the 68000, called IPL0, IPL1, and IPL2. IPL stands for Interrupt Priority Level and each has a priority with 7 being the highest priority. These can be masked by the IPL bits in the status register. The interrupt priority is generated using a 74LS148 8 to 3 line encoder.
The non-maskable interrupt can be triggered using the J4 header on the PCB.
|1||Expansion slot 1|
|2||IDE interface interrupt|
|3||PIT timer interrupt|
|4||Serial port interrupt|
|5||Keyboard and mouse interrupt|
|6||Expansion slot 2|
|7||Expansion slot 3|
This page contains information for revision 3 of the board. Information for revision 2 can be found here.